Introduction to volume rendering
Introduction to volume rendering
A VLSI inner product macrocell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Reconfigurable parallel inner product processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive Computer Graphics: A Top-Down Approach With OPENGL primer package-2nd Edition
Interactive Computer Graphics: A Top-Down Approach With OPENGL primer package-2nd Edition
A run-time reconfigurable array of multipliers architecture
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
IEEE Transactions on Computers
Design and implementation of a high-speed matrix multiplier based on word-width decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the architecture, design and test of a unified arithmetic processor, developed based on recently proposed partial product bit-matrix decomposition and dynamic reconfiguration parallel processing mechanism.By trading bitwidth for array size, the processor is able to perform several operations involving the multiplieation of two 32-b numbers and two 4脳4 matriees of 8-b numbers, as well as the evaluation of the inner produet of two size-4 arrays of 16-b numbers. All of them are important to many applieations ineluding graphies and volume rendering.A set of very simple and effieient reconfigurable switches is utilized to aehieve the high performanee. Only two extra bits are needed for all reeonfiguration controls. The architecture also possesses a superiority for high quality test. The cireuit simulations with a 2.5V, 0.25碌 proeess have shown that the proeessor performanee including delay and VLSI area is comparable with the existing single-function counterparts.