Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
ISPDC '04 Proceedings of the Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
ISPDC '05 Proceedings of the The 4th International Symposium on Parallel and Distributed Computing
PDP '07 Proceedings of the 15th Euromicro International Conference on Parallel, Distributed and Network-Based Processing
Program Execution Control in a Multi CMP Module System with a Look-Ahead Configured Global Network
ISPDC '09 Proceedings of the 2009 Eighth International Symposium on Parallel and Distributed Computing
Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
Scheduling parallel programs based on architecture: supported regions
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part II
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Local and global communication between computing cores is an essential problem of efficient parallel computations in many---core massively parallel systems based on many Chip Multi---Processor (CMP) modules interconnected by global networks. The paper presents new methods for data communication inside and between CMP modules. At the level of data communication between CMP modules a special network implements communication between CMP module external shared memories with simultaneous reads on the fly to L2 data caches and main memories of CMP modules. Similar mechanism improves local communication between shared memory modules and data caches inside CMPs.