Multi-CMP system with data communication on the fly
The Journal of Supercomputing
Scheduling architecture---supported regions in parallel programs
PARA'10 Proceedings of the 10th international conference on Applied Parallel and Scientific Computing - Volume Part I
Data transfers on the fly for hierarchical systems of chip multi-processors
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
Scheduling parallel programs based on architecture: supported regions
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part II
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This special issue of IEEE Micro brings readers the latest advances in the field of on-chip interconnects for multicores. The guest editors specifically selected articles to focus on novel on-chip networks realized on actual silicon--partly to showcase a few silicon prototypes of on-chip networks being used in multicore processors and SoCs; partly to bring to attention the implementation issues facing architects and designers. Along with six articles that gather insights from the designers of actual on-chip interconnects for multicores, the special issue includes two articles that delve into the design infrastructure support for on-chip networks and an article that summarizes the grand research challenges for realizing next-generation on-chip networks and multicores.