Scheduling precedence graphs in systems with interprocessor communication times
SIAM Journal on Computing
Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
ISPDC '04 Proceedings of the Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
ISPDC '05 Proceedings of the The 4th International Symposium on Parallel and Distributed Computing
Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly
ISPDC '08 Proceedings of the 2008 International Symposium on Parallel and Distributed Computing
Interconnect-Centric Design for Advanced SOC and NOC
Interconnect-Centric Design for Advanced SOC and NOC
Scheduling moldable tasks for dynamic SMP clusters in soc technology
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
Data transfers on the fly for hierarchical systems of chip multi-processors
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
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Modern multicore processor technology can fairly easily deliver special accelerator processors dedicated to fast optimised execution of critical computational functions. Multi CMP (Chip Multi-Processor) systems can be composed as a set of dedicated and general purpose computational modules interconnected by a global data exchange network. The paper proposes special program scheduling algorithms for such systems. Dedicated CMP modules assumed in the paper are based on a new data communication model called communication on the fly. It enables strong reduction of inter---process and inter---core communication overheads for intensively shared data.