PPAM'09 Proceedings of the 8th international conference on Parallel processing and applied mathematics: Part II
Multi-CMP system with data communication on the fly
The Journal of Supercomputing
Scheduling architecture---supported regions in parallel programs
PARA'10 Proceedings of the 10th international conference on Applied Parallel and Scientific Computing - Volume Part I
Scheduling parallel programs based on architecture: supported regions
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part II
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The paper concerns program scheduling methods oriented towards "System on Chip" (SoC) -based modular parallel architectures with efficient features of inter-processor communication. In the assumed architecture, a global communication network connects many SoC modules in which SMP clusters are dynamically created at program run-time to provide transfers of shared data on the fly for many processors at a time. Programs are represented as extended macro data flow graphs, which adequately describe communication between processor data caches and shared memory modules. The proposed scheduling algorithm is composed of two phases. The first phase distributes program graph nodes among SoC modules, assuming full inter-processor connection networks. It is implemented as a genetic algorithm with internally embedded ETF heuristics. The second phase of the algorithm schedules computation and communication inside SoC modules, so as to optimally use dynamic processor switching between clusters and data read on the fly mechanisms. Scheduling results of sample program graphs evaluated using simulation methods illustrate the efficiency of the proposed algorithm.