Scheduling architecture---supported regions in parallel programs

Authors:
Marek Tudruj;Łukasz Ma$#347;ko
Affiliations:
Institute of Computer Science of the Polish Academy of Sciences, Warsaw, Poland;Institute of Computer Science of the Polish Academy of Sciences, Warsaw, Poland
Venue:
PARA'10 Proceedings of the 10th international conference on Applied Parallel and Scientific Computing - Volume Part I
Year:
2010

Citing 10
Cited 0

Scheduling precedence graphs in systems with interprocessor communication times

SIAM Journal on Computing
Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs

Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Approximation Algorithms for Scheduling Malleable Tasks under Precedence Constraints

ESA '01 Proceedings of the 9th Annual European Symposium on Algorithms
Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations

ISPDC '04 Proceedings of the Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
Towards Massively Parallel Numerical Computations Based on Dynamic SMP Clusters with Communication on the Fly

ISPDC '05 Proceedings of the The 4th International Symposium on Parallel and Distributed Computing
Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology

PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
Guest Editors' Introduction: On-Chip Interconnects for Multicores

IEEE Micro
Research Challenges for On-Chip Interconnection Networks

IEEE Micro
Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly

ISPDC '08 Proceedings of the 2008 International Symposium on Parallel and Distributed Computing
Scheduling moldable tasks for dynamic SMP clusters in soc technology

PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current multicore system technology enables implementation of particular program functions like library operations, special functions generation, optimized data search etc. using dedicated computing units to increase overall program performance. A parallel system can be equipped with a set of such units to speed up execution of applications, which use such functionality. To properly model and schedule programs using such functions running on a dedicated hardware, a proper program representation must be introduced. The paper presents special scheduling algorithm for programs represented as graphs, based on a modified ETF heuristics. The algorithm is meant for a modular architecture composed of many CMP modules interconnected by a global data communication network. The assumed architecture of dedicated CMP modules enables personalized fully synchronous program execution, which uses communication on the fly to strongly reduce inter---core communication overheads.