A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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A Network on Chip Architecture and Design Methodology
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×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
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System on Chip (SoC) design faces several challenges which are due to the extremely small nature of electronic devices and the consequent opportunity to realize multi-processing systems of extremely high complexity. To manage large scale design, SoCs are assembled out of complex standard parts, such as programmable cores and memory arrays. Thus, the major design challenge is to provide correct and reliable operation of the interconnected components. Top-down correct component interconnection will become increasingly harder to succeed, because the interface features of components will also scale-up in complexity. New design methodologies will need to leverage component self-configuration and adaptation to the underlying communication fabric.