Memory system energy (poster session): influence of hardware-software optimizations

Authors:
G. Esakkimuthu;N. Vijaykrishnan;M. Kandemir;M. J. Irwin
Affiliations:
Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA;Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA;Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA;Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

Citing 7
Cited 10

Cache design trade-offs for power and performance optimization: a case study

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analytical energy dissipation models for low-power caches

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving locality using loop and data transformations in an integrated framework

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy-driven integrated hardware-software optimizations using SimplePower

Proceedings of the 27th annual international symposium on Computer architecture
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design

Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
High Performance Compilers for Parallel Computing

High Performance Compilers for Parallel Computing

Compiler support for block buffering

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Automatic source code specialization for energy reduction

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Morphable Cache Architectures: Potential Benefits

OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Source code transformation based on software cost analysis

Proceedings of the 14th international symposium on Systems synthesis
A Holistic Approach to System Level Energy Optimization

PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Compiler optimizations for low power systems

Power aware computing
Packetization and routing analysis of on-chip multiprocessor networks

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Improving the energy behavior of block buffering using compiler optimizations

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints

Integration, the VLSI Journal
Instruction Hints for Super Efficient Data Caches

ICCS 2009 Proceedings of the 9th International Conference on Computational Science

Quantified Score

Hi-index	0.00

Visualization

Abstract

Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms (block buffering and sub-banking) and three widely used compiler optimization techniques (linear loop transformation, loop tiling, and loop unrolling). Our results show that the pure hardware optimizations (eight block buffers and four sub-banks in a 4K, 2-way cache) provided up to 4% energy saving, with an average saving of 2% across all benchmarks. In contrast, the pure software optimization approach that uses all three compiler optimizations, provided at least 23% energy saving, with an average of 62%. However, a closer observation reveals that hardware optimization becomes more critical for on-chip cache energy reduction when executing optimized codes.