Compiler optimizations for low power systems

  • Authors:

  • Mahmut Kandemir;N. Vijaykrishnan;Mary Jane Irwin

  • Affiliations:

  • Microsystems Design Lab, Pennsylvania State University, University Park, PA;Microsystems Design Lab, Pennsylvania State University, University Park, PA;Microsystems Design Lab, Pennsylvania State University, University Park, PA

  • Venue:
  • Power aware computing
  • Year:
  • 2002

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Abstract

Most current compiler optimizations focus on improving execution time. With the increasingly widespread use of embedded systems, however, power/energy consumption is also becoming an important issue. This is particularly true for battery-operated devices where power consumption has first class status along with performance and form factor.This paper makes the following contributions. First, we present two low-level (back-end) compiler optimizations for energy reduction. An important conclusion drawn from evaluating the impact of these optimizations is that compiling for power/energy is different from compiling for execution cycles. Second, we evaluate widely used state-of-the-art high-level compiler optimizations from a power consumption perspective. Further, we compare the relative impact of these high-level optimizations on both energy and performance metrics in order to identify any differences in optimizing for energy and performance. Finally, we cover a set of optimizations that are designed specifically for exploiting low power features supported by the hardware. In particular, we show how loop and data transformation can be used to exploit low-power mode control mechanisms available in some memory architectures.