On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Self-Similar Network Traffic and Performance Evaluation
Self-Similar Network Traffic and Performance Evaluation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
Modeling and Performance Analysis of Self-Similar Traffic Based on FBM
NPC '07 Proceedings of the 2007 IFIP International Conference on Network and Parallel Computing Workshops
On Generating Self-Similar Network Traffic Using Multi-core Processors
ISCSCT '08 Proceedings of the 2008 International Symposium on Computer Science and Computational Technology - Volume 01
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power NoC for High-Performance SoC Design
Low-Power NoC for High-Performance SoC Design
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
Effect of Application Mapping on Network-on-Chip Performance
PDP '12 Proceedings of the 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the use of fractional Brownian motion in the theory of connectionless networks
IEEE Journal on Selected Areas in Communications
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
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Networks-on-chip (NoC) is a promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, such as networking, embedded design and computer architecture. Application mapping is one of these problems, which is generally considered in the form of a communication energy minimization problem. Self similarity is a traffic model that is used to characterize Ethernet and/or wide area network traffic, as well as on-chip network traffic. The present paper tackles the application mapping problem from a networking point of view using self similar traffic assumption and aims to find a mapping solution that improves network performance in terms of buffer utilization while simultaneously minimizing the total communication energy consumption. In this study, by using a self similar on-chip traffic characterization, an application mapping problem definition, which contains both energy and buffer utilization concerns is proposed. In order to solve this intractable problem, a genetic algorithm based solution is derived and implemented. Execution of the algorithm on different test cases has proven that such a mapping formulation avoids high buffer over utilizations while keeping the communication energy requirement still low.