Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Introducing robustness in multi-objective optimization
Evolutionary Computation
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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The current technological defect densities and production yields are a motivating factor supporting the introduction of design-for-manufacturability techniques during the high-level design of complex, embedded systems based on network-on-chips (NoCs). In this context, we tackle the problem of mapping the IPs of a multi-processing system to the NoC nodes, by taking into account the effective robustness of the system with respect to permanent faults in the interconnection network due to manufacturing defects. In particular, we introduce an application specific methodology for identifying optimal NoCs mappings which minimize the variance of the system power and latency and maximizes the probability that the actual system will work when deployed, even in presence of faulty NoC links. We provide experimental results by comparing the proposed methodology with conventional mapping approaches, by highlighting benefits and drawbacks of both techniques.