Proceedings of the 6th international workshop on Hardware/software codesign
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Mapping Intellectual Property (IP) cores onto a Network-on-Chip (NoC) architecture is an important phase of NoC design and the performance and energy consumption of the chip are the major issues that affect the design. In this paper, we analyze the preexistent mapping algorithms and present a new efficient energy and bandwidth aware topological mapping of IPs onto regular tile-based NoC architecture. The proposed algorithm has been implemented and evaluated for randomly generated benchmarks as well as real-life applications like Video Object Plane Decoder (VOPD) and Telecom. The experimental results have also been compared with existing mapping algorithms for the same set of benchmarks which clearly demonstrate significant reduction in maximum allocated bandwidth and energy for future NoC architectures with large number of IP cores. Further, there is a significant reduction in execution time of the proposed algorithm as compared to the other techniques.