A multi-processor NoC-based architecture for real-time image/video enhancement

Authors:
Sergio Saponara;Luca Fanucci;Esa Petri
Affiliations:
Department of Information Engineering, University of Pisa, Pisa, Italy 56122;Department of Information Engineering, University of Pisa, Pisa, Italy 56122;Consorzio Pisa Ricerche scarl, Pisa, Italy 56125
Venue:
Journal of Real-Time Image Processing
Year:
2013

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Abstract

The paper presents a multi-processor architecture for real-time and low-power image and video enhancement applications. Differently from other state-of-the-art parallel architectures the proposed solution is composed of heterogeneous tiles. The tiles have computational and memory capabilities, support different algorithmic classes and are connected by a novel Network-on-Chip (NoC) infrastructure. The proposed packet-switched data transfer scheme avoids communication bottlenecks when more tiles are working concurrently. The functional performances of the NoC-based multi-processor architecture are assessed by presenting the achieved results when the platform is programmed to support different enhancement algorithms for still images or videos. The implementation complexity of the NoC-based multi-tile platform, integrated in 65 nm CMOS technology, is reported and discussed.