Fundamentals of digital image processing
Fundamentals of digital image processing
Polynomial and rational operators for image processing and analysis
Nonlinear image processing
Adaptive block matching motion estimation algorithm using bit-plane matching
ICIP '95 Proceedings of the 1995 International Conference on Image Processing (Vol. 3)-Volume 3 - Volume 3
Optimization Techniques for ADL-Driven RTL Processor Synthesis
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Design of a Configurable Embedded Processor Architecture for DSP Functions
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Pedestrian Detection with Stereo Vision
ICDEW '05 Proceedings of the 21st International Conference on Data Engineering Workshops
Application Specific Instruction Set Processor for Adaptive Video Motion Estimation
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Design space exploration of partially re-configurable embedded processors
Proceedings of the conference on Design, automation and test in Europe
A compact integrated visual motion sensor for ITS applications
IEEE Transactions on Intelligent Transportation Systems
Video-based lane estimation and tracking for driver assistance: survey, system, and evaluation
IEEE Transactions on Intelligent Transportation Systems
Properties and performance of a center/surround retinex
IEEE Transactions on Image Processing
IEEE Transactions on Circuits and Systems for Video Technology
Application specific instruction-set processor template for motion estimation in video applications
IEEE Transactions on Circuits and Systems for Video Technology
Two-bit transform for binary block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Constrained One-Bit Transform for Low Complexity Block Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
A multi-processor NoC-based architecture for real-time image/video enhancement
Journal of Real-Time Image Processing
Journal of Real-Time Image Processing
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The paper presents a novel technique for robust motion analysis in real automotive scenarios based on integrated Retinex-like pre-processing algorithm with block matching video motion estimator. Both algorithmic and real-time hardware design issues are discussed. The benefits of the proposed technique are manifold: the entire system is more robust; the estimated motion vectors are more reliable and less dependent on critical ambient conditions like shadows or flashes; the proposed algorithm may allow to perform motion estimation using very few bits and running as a 2- or 1-bit transform, still maintaining good performances. Real-time hardware implementation is achieved by design and synthesis in 65聽nm CMOS standard-cells technology of an Application Specific Instruction-set Processor. Design optimizations for both the processing core and the memory organization are presented. With respect to the state of the art the proposed hardware implementation ensures bounded circuit complexity, low power consumption and reprogrammability of the technique.