Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems
International Journal of Handheld Computing Research
A multi-processor NoC-based architecture for real-time image/video enhancement
Journal of Real-Time Image Processing
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Cost-effective handheld graphics processing units are discussed in the aspects of performance, memory bandwidth, power, and area requirements. The proposed RamP architecture has special features of cost-effective low-power arithmetic units, memory bandwidth reduction, and dynamic power management schemes for handheld GPUs. The detailed design of RamP- VI is explained as an example of the RamP architecture. It adopts logarithmic arithmetic for power and area efficiency, and has a triple- domain power management scheme to minimize power consumption at a given performance level. The proposed GPU shows peak performance of 141 Mvertices/s and 52.4 mW power consumption when it operates at 60 frames/s. It shows 17.5 percent performance improvement and 50.5 percent power reduction compared to the latest work.