JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Very Long Instruction Word Architectures for Digital Signal Processing
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Vector processing in scalar processors for signal processing algorithms
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Multidimensional rational approximations with an application to linear transforms
IEEE Transactions on Signal Processing
Fast multiplierless approximations of the DCT with the liftingscheme
IEEE Transactions on Signal Processing
Fast image transforms using diophantine methods
IEEE Transactions on Image Processing
| Hi-index | 0.00 |
Wide computer registers offer opportunities to exploit parallel processing. Instead of using hardware assists to partition a register into independent noninteracting fields, the multiple data elements can borrow and carry from elements to the left, and yet be accurately separated. Algorithms can be designed so that they execute within the allocated precision. Their floating point or irrational constants (e.g., cosines) are converted into integer numerators with floating point denominators. The denominators are then merged into scaling terms. To control the dynamic range and thus require less bits of precision per element, shift rights can be used. The effect of the average truncation errors is analyzed and a technique shown to minimize this average error.