Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
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DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
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Signal and image processing with neural networks: a C++ sourcebook
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IEEE Design & Test
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VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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ACM SIGSAM Bulletin
ICML '06 Proceedings of the 23rd international conference on Machine learning
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IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Expert Systems with Applications: An International Journal
Input-state approach to boolean networks
IEEE Transactions on Neural Networks
| Hi-index | 12.05 |
In this paper, we present the feed-forward neural network (FFNN) and recurrent neural network (RNN) models for predicting Boolean function complexity (BFC). In order to acquire the training data for the neural networks (NNs), we conducted experiments for a large number of randomly generated single output Boolean functions (BFs) and derived the simulated graphs for number of min-terms against the BFC for different number of variables. For NN model (NNM) development, we looked at three data transformation techniques for pre-processing the NN-training and validation data. The trained NNMs are used for complexity estimation for the Boolean logic expressions with a given number of variables and sum of products (SOP) terms. Both FFNNs and RNNs were evaluated against the ISCAS benchmark results. Our FFNNs and RNNs were able to predict the BFC with correlations of 0.811 and 0.629 with the benchmark results, respectively.