An entropy measure for the complexity of multi-output Boolean functions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Accurate area and delay estimation from RTL descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
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Early power estimation requires one to estimate the area (gate count) of a design from a high-level description. We propose a method to do this that makes use of the concept of Boolean networks (BN) and introduces an invariant area complexity measure which captures the gate-count requirement of a design. The method can be adapted to be used at different points on the area/delay tradeoff curve, with different synthesizer/mapper tools, and different target gate libraries. The area model is experimentally verified and tested using a number of ISCAS and MCNC benchmark circuits and two different target cell libraries, on two different synthesis systems.