Numerical recipes in C: the art of scientific computing
Numerical recipes in C: the art of scientific computing
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Basis Sets for Synthesis of Switching Functions
IEEE Transactions on Computers
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Delay estimation VLSI circuits from a high-level view
DAC '98 Proceedings of the 35th annual Design Automation Conference
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 2002 international symposium on Low power electronics and design
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In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impact of behavioral modifications, resulting in significant savings in design schedule.