Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The complexity of Boolean functions
The complexity of Boolean functions
Signal and image processing with neural networks: a C++ sourcebook
Signal and image processing with neural networks: a C++ sourcebook
Circuit complexity and neural networks
Circuit complexity and neural networks
Introduction to neural networks
Introduction to neural networks
Discrete neural computation: a theoretical foundation
Discrete neural computation: a theoretical foundation
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
On the Complexity of Constructing Optimal Ordered Binary Decision Diagrams
MFCS '94 Proceedings of the 19th International Symposium on Mathematical Foundations of Computer Science 1994
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Evaluation time Estimation for Pass Transistor Logic circuits
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
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This paper describes a neural network approach that gives an estimation method for the space complexity of Binary Decision Diagrams (BDDs). A model has been developed to predict the complexity of digital circuits. The formal core of the developed neural network model (NNM) is a unique matrix for the complexity estimation over a set of BDDs derived from Boolean logic expressions with a given number of variables and Sum of Products (SOP) terms. Experimental results show good correlation between the theoretical results and those predicted by the NNM, which will give insights to the complexity of Very Large Scale Integration (VLSI)/Computer Aided Design (CAD) designs. The proposed model is capable of predicting the maximum BDD complexity (MaxBC) and the number of product terms (NPT) in the Boolean function that corresponds to the minimum BDD complexity (MinBC). This model provides an alternative way to predict the complexity of digital VLSI circuits.