Evaluation time Estimation for Pass Transistor Logic circuits

Authors:
P. W. C. Prasad;B. I. Mills;A. Assi;S. M. N. A. Senanayake;V. C. Prasad
Affiliations:
UAE University, UAE;UAE University, UAE;UAE University, UAE;Monash University, Malaysia Campus, Malaysia;Multimedia University, Malaysia
Venue:
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
Year:
2006

Citing 0
Cited 2

Binary Decision Diagrams and neural networks

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Binary decision diagrams: a mathematical model for the path-related objective functions

SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization

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Abstract

This paper describes a mathematical model for the prediction of Binary Decision Diagram (BDD) depth measures, such as the Longest Path Length (LPL) and the Average Path Length (APL). The formal core of the model is a formula for the average LPL and APL over the set of BDD derived from Boolean logic expressions with a given number of variables and product terms. The formula was determined by extensive empirical studies of these measures. The proposed model can provide valuable information about Pass Transistor Logic (PTL) evaluation time for any variable ordering method without building the BDD. Our experimental results show good correlation between the theoretical results and those predicted by the mathematical model, which will greatly reduce the time complexity of applications that use BDDs.