Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
Decision Diagrams and Pass Transistor Logic Synthesis
Decision Diagrams and Pass Transistor Logic Synthesis
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DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Evaluation time Estimation for Pass Transistor Logic circuits
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
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This paper describes a mathematical model for all path length parameters (APL: Average Path Length, LPL: Longest Path Length, and SPL: Shortest Path Length) of Binary Decision Diagrams (BDDs). The proposed model is based on an empirical analysis of randomly generated Boolean functions. The formal core of the developed model is a unique equation for the path-related objective functions over the set of BDDs derived from Boolean functions with given number of variables and Sum of Products (SOP) terms. Simulation results show good correlation between the theoretical results and those predicted by the mathematical model. This model provides an estimation of the performance of a circuit prior to its final implementation, and can be applied to Boolean functions with any number of variables, any number of product terms, and any variable ordering method.