Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Improving the accuracy of circuit activity measurement
DAC '94 Proceedings of the 31st annual Design Automation Conference
Improving the efficiency of power simulators by input vector compaction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hierarchical sequence compaction for power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power invariant vector sequence compaction
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On the approximability of minimizing nonzero variables or unsatisfied relations in linear systems
Theoretical Computer Science
Feature Selection via Concave Minimization and Support Vector Machines
ICML '98 Proceedings of the Fifteenth International Conference on Machine Learning
Use of the zero norm with linear models and kernel methods
The Journal of Machine Learning Research
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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This paper presents an algorithm for compressing long traces generated using RTL or other fast simulation. The compressed traces can be used by power analysis tools to estimate power on the original traces. We show that the length of the compressed trace is independent of the length of original trace and is a function of circuit size (precisely, its active part) for which the trace was generated. Our experiments show up to 578x compression ratio on several long RTL traces (up to 320,000 clock transitions) used for power analysis on three industrial blocks (4K, 114K and 202K gates). This leads to significant runtime improvement, especially when the traces are reused over multiple power analysis runs. The dynamic power estimated using compressed traces is within 5% of the power analysis on original traces.