Low-complexity reorder buffer architecture
ICS '02 Proceedings of the 16th international conference on Supercomputing
Energy-Efficient Design of the Reorder Buffer
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Energy-efficient issue queue design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
IEEE Transactions on Computers
Finding optimal L1 cache configuration for embedded systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Playing the trade-off game: Architecture exploration using Coffeee
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Proceedings of the 47th Design Automation Conference
DEW: a fast level 1 cache simulation approach for embedded processors with FIFO replacement policy
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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This paper describes the AccuPower toolset -- a set ofsimulation tools accurately estimating the powerdissipation within a superscalar microprocessor.AccuPower uses a true hardware level and cycle levelmicroarchitectural simulator and energy dissipationcoefficients gleaned from SPICE measurements of actualCMOS layouts of critical datapath components. Transitioncounts can be obtained at the level of bits within data andinstruction streams, at the level of registers, or at the levelof larger building blocks (such as caches, issue queue,reorder buffer, function units). This allows for an accurateestimation of switching activity at any desired level ofresolution.