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Power consumption in processors have become a major issue in these days. This paper considers an efficient technique of serializing the datapath to reduce the power consumption as in [1]. We use the 64 bit datapath of Sun OpensSPARC T1 processor. This processor has four basic blocks for data manipulations which along with the register file and the bypass logic forms the datapath. Serialization is applied to all the four blocks which are the shift, multiply, divide, and Arithmetic and Logic (ALU) blocks. Power estimation and analysis are done for ALU and multiply blocks. We have introduced a module called serializer which is included as part of the bypass logic, to serialize the data path. Serializing can be brought about without much compromise in the speed but this paper emphasizes on the reduction in power consumption. The modified, bit serialized datapath of OpenSPARC T1 is implemented in Verilog HDL. Power analysis of original, parallel datapath and the modified, bit serialized datapath designs of OpenSPARC is done using Xilinx ISE 10.1 Power Analyzer. The results are discussed at the end of this paper.