Combinatorial theory (2nd ed.)
Combinatorial theory (2nd ed.)
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel global placement with congestion control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
A combinatorial congestion estimation approach with generalized detours
Computers & Mathematics with Applications
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Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and routability. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach which allows wires to have bounded-, length detours to bypass congestions. Our method is more realistic and precise than the previous work. It is much faster than a global router for estimation purpose. The experimental results demonstrate the effectiveness of the method on routing benchmarks.