Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Stress-Aware Design Methodology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
STEEL: a technique for stress-enhanced standard cell library design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Closed-form modeling of layout-dependent mechanical stress
Proceedings of the 47th Design Automation Conference
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In nanometer technologies, shallow trench isolation (STI) induces thermal residual stress in active silicon due to post-manufacturing thermal mismatch. The amount of STI around an active region depends on the layout of the design, and the biaxial stress due to STI results in placement-dependent variations in the the transistor mobilities and threshold voltages of the active devices. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement.