Fill for shallow trench isolation CMP
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
Exploiting STI stress for performance
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
VEBoC: variation and error-aware design for billions of devices on a chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
The impact of shallow trench isolation effects on circuit performance
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations.