Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Analytical minimization of half-perimeter wirelength
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Improved cut sequences for partitioning based placement
Proceedings of the 38th annual Design Automation Conference
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
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We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms were developed based on a single local optimization function, called the sequential cut line objective function. Our algorithm incorporates global objective functions into this traditional framework of min-cut placement. In particular, we introduce a new global objective function based on the congestions for cut lines and use it for the selection of their sequence. We also use the total cut value objective function in the determination of the sizes and connectivities of clusters that are to be used in the early stages of min-cut partitioning. The incorporation of such global objective functions yields additional reductions of wire congestions in the entire as well as local chip areas. With the automatic selection and use of such clusters and a cut line sequence, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips of 1.5 K to 150 K raw gates