Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Generalization of Min-Cut Partitioning to Tree Structures and its Applications
IEEE Transactions on Computers
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Models for iterative global optimization
Models for iterative global optimization
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Network partitioning into tree hierarchies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Nostradamus: a floorplanner of uncertain design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization by iterative improvement: an experimental evaluation on two-way partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
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The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing and placement optimization. Formulations or optimization objectives for partitioning follow from its context and role. Finally, the available algorithm technology determines how effectively we can address a given partitioning formulation and optimize a given objective. This invited paper considers the future of partitioning for physical design in light of these factors, and proposes a list of technology needs. A living version of this paper can be found at vlsicad.cs.ucla.edu.