Relaxation techniques for the simulation of VLSI circuits
Relaxation techniques for the simulation of VLSI circuits
Partitioning the nodes of a graph
Graph theory with applications to algorithms and computer science
A new heuristic for partitioning the nodes of a graph
SIAM Journal on Discrete Mathematics
ACM Transactions on Mathematical Software (TOMS)
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Finding good approximate vertex and edge partitions is NP-hard
Information Processing Letters
Vertex and edge partitions of graphs
Vertex and edge partitions of graphs
Optimal Sequential Partitions of Graphs
Journal of the ACM (JACM)
Computer Solution of Large Sparse Positive Definite
Computer Solution of Large Sparse Positive Definite
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A study of the effect of user program optimization in a paging system
SOSP '67 Proceedings of the first ACM symposium on Operating System Principles
ON BISECTING RANDOM GRAPHS
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning
IEEE Transactions on Computers
A new effective and efficient multi-level partitioning algorithm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combinatorial Optimization by Dynamic Contraction
Journal of Heuristics
A Fast and Effective Algorithm for the Feedback Arc Set Problem
Journal of Heuristics
Randomized Algorithms: A System-Level, Poly-Time Analysis of Robust Computation
IEEE Transactions on Computers
Investigation of the Fitness Landscapes in Graph Bipartitioning: An Empirical Study
Journal of Heuristics
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
IEEE Transactions on Computers
Algorithmic aspects of hardware/software partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding optimal hardware/software partitions
Formal Methods in System Design
Investigation of the fitness landscapes and multi-parent crossover for graph bipartitioning
GECCO'03 Proceedings of the 2003 international conference on Genetic and evolutionary computation: PartI
Hi-index | 14.99 |
Partitioning is a fundamental problem in diverse fields of study such as pattern recognition, parallel processing, and the design of VLSI circuits. Recently, node clustering or compaction has been shown to enhance the performance of iterative partitioning algorithms by several authors. However, clustering has been mainly used as a preprocessing step before partitioning in existing methods. This paper describes a technique to extract clusters using information collected during a pass of an iterative exchange algorithm. Alternative approaches for the implementation of this new clustering technique are discussed, and one such approach is chosen to be incorporated in a modified Fiduccia-Mattheyses algorithm based on a tradeoff between run time and performance. The resulting algorithm, BISECT, performs well in comparison with variants of the Kernighan-Lin algorithm including the Fiduccia-Mattheyses algorithm, local approaches, and simulated annealing on a wide variety of real and randomly generated benchmarks. BISECT is also used to find small vertex separators, and its results are compared with previous methods on several benchmarks. The empirical results show that BISECT is stable and is not very sensitive to the initial partition. Under suitably mild assumptions, BISECT can be shown to run in linear time. The empirical results confirm the speed of BISECT which can partition very large graphs (12,598 nodes and 91,961 edges) in less than six minutes of CPU time on a Sun Sparc 1+ workstation.