Simulated annealing: theory and applications
Simulated annealing: theory and applications
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Linear decomposition algorithm for VLSI design applications
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Local Search in Combinatorial Optimization
Local Search in Combinatorial Optimization
Iterative improvement based multi-way netlist partitioning for FPGAs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
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An algorithm that remains in use at the core of many partitioning systems is the Kernighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM algorithm we applied principles of data engineering where visualization and statistical analysis are used to analyze the run-time behavior. We identified two improvements to the algorithm which, without clustering or an improved heuristic function, bring the performance of the algorithm near that of more sophisticated algorithms. One improvement is based on the observation, explored empirically, that the full passes in the FM algorithm appear comparable to a stochastic local restart in the search. We motivate this observation with a discussion of recent improvements in Monte Carlo Markov Chain methods in statistics. The other improvement is based on the observation that when an FM-like algorithm is run 20 times and the best run chosen, the performance trace of the algorithm on earlier runs is useful data for learning when to abort a later run. These improvements, implemented with a simple adaptive scheme, are orthogonal to techniques used in state-of-the-art implementations, and should therefore be applicable to other VLSI optimization algorithms.