Multiple-Way Network Partitioning
IEEE Transactions on Computers
Net partitions yield better module partitions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Geometric embeddings for faster and better multi-way netlist partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
A new approach to effective circuit clustering
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multi-way partitioning of VLSI circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Hypergraph Partitioning-Based Fill-Reducing Ordering for Symmetric Matrices
SIAM Journal on Scientific Computing
Partitioning Hypergraphs in Scientific Computing Applications through Vertex Separators on Graphs
SIAM Journal on Scientific Computing
An improved parameterized algorithm for the minimum node multiway cut problem
WADS'07 Proceedings of the 10th international conference on Algorithms and Data Structures
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In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN). Given a netlist, we first compute a K-way partition of the nets based on the HDN representation, and then transform a K-way net partition into a K-way module partitioning solution. The main contribution of our work is the formulation and solution of the K-way module contention (K-MC) problem, which determines the best assignment of the modules in contention to partitions, while maintaining user-specified area requirements, when we transform the net partition into a module partition. Under a natural definition of binding factor between nets and modules, and preference function between partitions and modules, we show that the K-MC problem can be reduced to a min-cost max-flow problem. We present efficient solutions to the K-MC problem based on network flow computation. Extensive experimental results show that our algorithm consistently outperforms the conventional K-FM partitioning algorithm by a significant margin.