Multiple-Way Network Partitioning
IEEE Transactions on Computers
Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ASG: automatic schematic generator
Integration, the VLSI Journal
Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New faster Kernighan-Lin-type graph-partitioning algorithms
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Arc crossing minimization in hierarchical digraphs with tabu search
Computers and Operations Research
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An Evaluation of Move-Based Multi-Way Partitioning Algorithms
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Level Assignment for Displaying Combinational Logic
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Interactive circuit diagram visualization
CGIM '08 Proceedings of the Tenth IASTED International Conference on Computer Graphics and Imaging
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In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g., more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four.