MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
System-in-package (SIP): challenges and opportunities
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Compiler-directed thermal management for VLIW functional units
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
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DRAM is usually used as main memory for program execution. The thermal behavior of a memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system, while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware memory allocator should consider the following two points. First, the allocator should consider not only the power behavior of a logic block but also the physical location during memory mapping and second, the changing temperature of a physical block during execution of programs. In this article, we will propose a memory mapping algorithm taking into consideration these two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that for single-core systems, our method can reduce the temperature of memory system by 17.1°C, as compared to a straightforward mapping in the best case, and 13.3°C on average. For systems with four cores, the temperature reductions are 9.9°C and 11.6°C on average when L1 cache of each core is set to 4KB and 8KB, respectively.