Improving data locality with loop transformations
ACM Transactions on Programming Languages and Systems (TOPLAS)
Precise miss analysis for program transformations with caches of arbitrary associativity
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Influence of compiler optimizations on system power
Proceedings of the 37th Annual Design Automation Conference
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Interprocedural Array Remapping
PACT '97 Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques
Static Energy Reduction Techniques for Microprocessor Caches
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
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Performance and energy consumption behavior of embedded applications are increasingly being dependent on their memory usage/access patterns. Focusing on a software-managed, application-specific multi-level memory hierarchy, this paper studies three different memory hierarchy management schemes from both energy and performance angles. The first scheme is pure performance-oriented and tuned for extracting the maximum performance possible from the software-managed multi-level memory hierarchy. The second scheme is built upon the first one but it also reduces leakage by turning-on and off memory modules (i.e., different memory levels) at appropriate program points during execution based on the data access pattern information extracted by the compiler. The last scheme evaluated is oriented towards further reducing leakage energy, as well as dynamic energy, by modifying the data transfer policy (data access pattern) of the performance-oriented scheme. Our empirical analysis indicates that it is possible to reduce leakage consumption of the application-specific multi-level memory hierarchy without seriously impacting its performance, and that one can achieve further savings by modifying data transfer pattern across the different levels of the memory hierarchy.