Low-power data memory communication for application-specific embedded processors
Proceedings of the 15th international symposium on System Synthesis
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic techniques to reduce memory traffic in embedded systems
Proceedings of the 1st conference on Computing frontiers
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reprogrammable customization framework for efficient branch resolution in embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Compiler-managed partitioned data caches for low power
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Miss reduction in embedded processors through dynamic, power-friendly cache design
Proceedings of the 45th annual Design Automation Conference
Performance and energy efficient cache migrationapproach for thermal management in embedded systems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Energy-optimized on-chip networks using reconfigurable shortcut paths
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Run-time reconfiguration of expandable cache for embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural features of modern embedded processors. The automated methodology for. customizing the processor microarchitecture that we propose results in increased performance, reduced power consumption and improved determinism of critical system parts while the fixed design ensures processor standardization. The resulting improvements help to enlarge the significant role of embedded processors in modern hardware-software codesign techniques by leading to increased processor utilization and reduced hardware cost. A novel methodology for static analysis and a microarchitecturally field-reprogrammable implementation of a customizable cache controller that implements a partitioned cache structure is proposed. Partitioning the load/store instructions eliminates cache interference; hence, precise knowledge about the hit/miss behavior of the references within each partition becomes available, resulting in significant reduction in tag reads and comparisons. Moreover, eliminating cache interference naturally leads to a significant reduction in the miss rate. The paper presents an algorithm for defining cache partitions, hardware support for customizable cache partitions, and a set of experimental results. The experimental results indicate significant improvements in both power consumption and miss rate