A data locality optimizing algorithm
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Applied Numerical Methods with Software
Applied Numerical Methods with Software
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
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The instruction memory communication path constitutes a significant amount of power consumption in embedded processors. We propose an encoding technique that exploits application information to reduce the associated power consumption. The microarchitectural support enables reprogrammability of the encoding transformations so as to track code particularities effectively. The restriction to functional transformations enables effective coding while delivering major power savings, in the process obviating furthermore the necessity to rely on dictionary lookup, one of the major shortcomings of prior approaches. The frugal functional transformation, reliant on a single bit logic gate, introduces no impact to the critical fetch stage of the processor pipeline while delivering fully all the theoretically achievable power savings. The reprogrammable hardware implementation enables flexible and inexpensive switches between the transformations. Extensive experimental results on numerical and DSP codes confirm the theoretically expected magnitude of power savings, evincing reductions that range up to half of the original transitions.