Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power encodings for global communication in CMOS VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Irredundant address bus encoding for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
Performance Analysis of On-Chip Communication Structures under Device Variability
International Journal of Embedded and Real-Time Communication Systems
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On-chip source-synchronous serial communication has many advantages over multi-bit parallel communication in the aspects of skew, crosstalk area cost, wiring difficulty, and clock synchronization. However, the serial wire tends to dissipate more energy than parallel bus due to the bit multiplexing. We propose a coding method to reduce the transmission energy of the serial communication by minimizing the number of transitions on the serial wire. We demonstrate the significant energy saving in a multimedia application, 3D graphics. We also apply the coding technique to a CMOS SoC implementation which integrates various processing units with packet switched on-chip networks.