Results on leakage power management in scratchpad-based embedded systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Increasing use of scratch-pad memories (SPMs) in embedded systems makes it imperative to consider optimizations tailored to their needs. Since these memories are managed by software, they present unique opportunities to the designer/compiler writer as far as energy optimizations are concerned. This paper proposes and quantifies the benefits of a compiler-directed energy optimization scheme for banked SPMs used to store the data manipulated by an application program. In contrast to most of the prior efforts on SPMs, which focus mainly on performance and dynamic energy consumption, the approach proposed in this paper is leakage oriented. Specifically, it tries to reduce the amount of SPM space (the number of banks) used to strike a balance between leakage and dynamic energy savings, with the goal of minimizing the total energy consumption due to data accesses. This paper presents an ILP (integer linear programming) based formulation of this problem and evaluates the proposed approach using a set of eight embedded application codes.