Hierarchical Instruction Register Organization

Authors:
David Black-Schaffer;James Balfour;William Dally;Vishal Parikh;JongSoo Park
Affiliations:
Stanford University, Stanford;Stanford University, Stanford;Stanford University, Stanford;Stanford University, Stanford;Stanford University, Stanford
Venue:
IEEE Computer Architecture Letters
Year:
2008

Citing 0
Cited 2

Fine-grain dynamic instruction placement for L0 scratch-pad memory

CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems

Journal of Signal Processing Systems

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Abstract

This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient Filter Cache.