Instruction level energy modeling for pipelined processors

Authors:
S. Nikolaidis;N. Kavvadias;T. Laopoulos;L. Bisdounis;S. Blionas
Affiliations:
Department of Physics, Aritstotle University of Thessaloniki, 54124 Thessaloniki, Greece (Corresponding author. Tel.: +30 2310 998078/ Fax: +30 2310 998018/ E-mail: snikolaid@physics.auth.gr);Department of Physics, Aritstotle University of Thessaloniki, 54124 Thessaloniki, Greece;Department of Physics, Aritstotle University of Thessaloniki, 54124 Thessaloniki, Greece;INTRACOM S.A., Peania, Greece;INTRACOM S.A., Peania, Greece
Venue:
Journal of Embedded Computing - Low-power Embedded Systems
Year:
2005

Citing 7
Cited 2

Power analysis of embedded software: a first step towards software power minimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Instruction level power analysis and optimization of software

Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Power analysis and minimization techniques for embedded DSP software

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors

OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instrumentation Set-up for Instruction Level Power Modeling

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors

ICCD '98 Proceedings of the International Conference on Computer Design

Rapid software power estimation of embedded pipelined processor through instruction level power model

SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
A precise high-level power consumption model for embedded systems software

EURASIP Journal on Embedded Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.