Power estimation of embedded systems: a hardware/software codesign approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Instruction Level Power Analysis and Optimization of Software
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
Instruction level energy modeling for pipelined processors
Journal of Embedded Computing - Low-power Embedded Systems
Power-efficient Instruction Encoding Optimization for Embedded Processors
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
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Embedded systems are characterized by the presence of a combination of dedicated processor and application specific software. With technological advances, although the number of transistors on a chip are increasing, the chip area is reducing thereby making power constraints a critical component of system design. In this paper, a scheme for efficient instruction level power profiling of an embedded processor is developed which incorporates a novel methodology to accurately determine the activity generated in the instruction stages of a pipelined processor. An accurate power model has been developed by using the associated net capacitances obtained from gate fanout values and the FPGA resource on which the respective nets are mapped. An open source LEON3 VHDL core has been employed at RTL level. An activity extraction tool has been developed that produces the activity count of each instruction from value change dump file produced by the simulator. To complement the power model, a capacitance extraction tool is also developed which takes mapping and routing information and gives the cumulative capacitance of each net. The activity count and associated capacitance of the nets provides a figure of merit for the power consumed by that instruction. Complete instruction set of LEON3 processor has been profiled in terms of power consumption. The corresponding power for any application is thus obtained instantaneously and consequently avoids low level power estimation overheads. Moreover, the effect as well as the dependence of instruction parameters such as operands and addresses on energy consumption has also been studied.