Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
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An attempt has been made to optimize the software energy of real time preemptive tasks by minimizing the cache related preemption costs which are primarily incurred due to the inter-task interference in the cache. We have presented an algorithm that outputs an "optimum" task layout which reduces the overall inter-task interference in cache and thus reduces the preemption costs of each task of a given task set. We have compared the result of our estimated layout with that of the random layout generated for benchmark examples for demonstrating the performance of our algorithm.