Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
Microarchitectural Synthesis Of ICs With Embedded Concurrent Fault Isolation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
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The introduction of high-level sophisticated mechanisms can bridge the gap in the field of safety-critical applications design and the low-power design. Two modified mechanisms that allow event driven operation with respect to safety requirements and on-line testing are presented. An optimized instruction-opcode mapping algorithm for application specific capable processing units is also introduced to assist the above mechanisms. The whole work has been applied to a commercial product and a 40% of power saving has been achieved.