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Effective partial redundancy elimination
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CC '99 Proceedings of the 8th International Conference on Compiler Construction, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'99
Code density optimization for embedded DSP processors using data compression techniques
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Optimal Code Motion in the Presence of Large Expressions
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
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ACM SIGPLAN Notices
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Optimizing for space and time usage with speculative partial redundancy elimination
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Combined code motion and register allocation using the value state dependence graph
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A fresh look at PRE as a maximum flow problem
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POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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In this article, we add a third dimension to partial redundancy elimination by considering code size as a further optimization goal in addition to the more classical consideration of computation costs and register pressure. This results in a family of sparse code motion algorithms coming as modular extensions of the algorithms for busy and lazy code motion. Each of them optimally captures a predefined choice of priority between these three optimization goals, e.g. code size can be minimized while (1) guaranteeing at least the performance of the argument program, or (2) even computational optimality. Each of them can further be refined to simultaneously reduce the lifetimes of temporaries to a minimum. These algorithms are well-suited for size-critical application areas like smart cards and embedded systems, as they provide a handle to control the code replication problem of classical code motion techniques. In fact, we believe that our systematic, priority-based treatment of trade-offs between optimization goals may substantially decrease development costs of size-critical applications: users may “play” with the priorities until the algorithm automatically delivers a satisfactory solution.