A New Framework for Integrated Global Local Scheduling

Using profiling to reduce branch misprediction costs on a dynamically scheduled processor

Proceedings of the 14th international conference on Supercomputing

On achieving balanced power consumption in software pipelined loops

CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures

IEEE Transactions on Computers

Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs

IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium

A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors

LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems

Speculative Prefetching of Induction Pointers

CC '01 Proceedings of the 10th International Conference on Compiler Construction

A Framework for Efficient Register Allocation through Selective Register Demotion

LCR '00 Selected Papers from the 5th International Workshop on Languages, Compilers, and Run-Time Systems for Scalable Computers

Integrated prepass scheduling for a Java Just-In-Time compiler on the IA-64 architecture

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization

Selective Guarded Execution Using Profiling on a Dynamically Scheduled Processor

IWIA '99 Proceedings of the 1999 International Workshop on Innovative Architecture

Register allocation by priority-based coloring

ACM SIGPLAN Notices - Best of PLDI 1979-1999

Queue Usage and Memory-Level Parallelism Sensitive Scheduling

HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region