Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
A power reduction technique with object code merging for application specific embedded processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Expression-tree-based algorithms for code compresion on embedded RISC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Efficient Approximate Adaptive Coding
DCC '97 Proceedings of the Conference on Data Compression
Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
Memory expansion technology (MXT): competitive impact
IBM Journal of Research and Development
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The redundancy available in binary programs presents an opportunity for better utilization of limited memory resources in systems-on-a-chip by compressing the instruction memory. Class-based coding, a form of approximate prefix coding, simplifies the code and thus is a suitable compression method for low-cost systems. We present a detailed frequency analysis of the SPEC2000 Alpha binary programs. Based on the results of this analysis, we introduce a new method for constructing classes. Then we apply this method and use it to compress the SPEC2000 Alpha binaries, and show that, in comparison with optimal prefix coding, the loss in compression efficiency is minimal. With some hardware support, the proposed method reduces the on-chip code by 43%.