Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The Microcore Development System ¾ A Unified Environment for Designing New Microprocessors
ICCD '98 Proceedings of the International Conference on Computer Design
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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This work presents a novel microprocessor architecture that was especially designed to reduce the power dissipation of modern systems-on-a-chip. The applications we aim at with this architecture are ultra-low-power embedded systems like intelligent medical implants or sensorized micro-transponders. We introduce new types of data storage files and hardware supported constant elimination to utilize the mostly local scope of common arithmetic operations for reducing energy. A multi-level instruction-cache scheme together with a cache controller supporting sophisticated opcode-preprocessing operations like Huffman-decoding decreases the amount of external memory accesses and size. Additionally the width of pointers is significantly reduced by a table-lookup cache-miss concept. Finally, a segmented gray-code address counter minimizes the transitions on external buses. All these concepts combine into a completely new type of microprocessor architecture, which is designed to reduce transitions per operation as much as possible.