Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A decompression core for powerPC
IBM Journal of Research and Development
Design of a decompressor engine on a SPARC processor
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A software-only compression system for trading-offs between performance and code size
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Huffman-based code compression techniques for embedded processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In the past, systems utilizing code compression have been shown to be advantageous over traditional systems especially in terms of smaller memory need. However, in order to take full advantage of other design criteria like increasing performance and/or minimizing power consumption, the decompression should take place as close as possible to the CPU. We have designed such a decompression unit that, in spite of the higher bandwidth constraints close to the CPU, does improve performance and minimize power consumption of a whole embedded system. By means of extensive simulations we have designed and eventually sized the various parameters of the decompression engine #pipelines, #pipeline stages, input/output buffer sizes etc.). As a result, the system's performance is increased by up to 46%. Unlike other approaches we have implemented our engine as a soft IP core such that it can be used directly within a SOC design without any modification on the CPU architecture.